The present invention relates to an output buffer circuit provided in a semiconductor integrated circuit (hereinafter, referred to as an IC).
A usual output buffer circuit is constituted by a complementary MOS transistor (hereinafter, referred to as CMOS) IC. An inverter is connected to an input terminal receiving an input signal. The inverter includes a P-channel type MOS transistor (hereinafter, referred to as PMOS) and an N-channel type MOS transistor (hereinafter, referred to as NMOS) which are connected in series between a power source potential VDD node and a ground potential VSS node (i.e., ground).
In designing an output buffer circuit, it is necessary to consider DC characteristics such as an output voltage and an output current of an output signal OUT. In order to satisfy the characteristics of the output voltage and output current, the PMOS and the NMOS are generally designed as large elements. However, when the PMOS and the NMOS have a large element size, rise and fall of the input signal IN causes a high-speed change of the rise and fall of the output signal OUT, generating an output waveform overshoot and undershoot. Moreover, for a short period of time, the PMOS and the NMOS simultaneously become an ON state, and a through current from the power source potential VDD to the ground potential VSS increases, causing problems that the power consumption increases and the power source noise also increases.
Thus, in the conventional output buffer circuit, it is difficult to suppress the change of the output signal OUT to a low speed while satisfying the DC characteristic.